1. Field of the Invention
The present invention relates to a design system, a design method and a computer program product for designing a layout of a semiconductor integrated circuit, particularly relates to the design system, the design method and the computer program product for designing a layout of the semiconductor integrated circuit using standard cells.
2. Description of the Related Art
Along with miniaturization of semiconductor integrated circuits, serious problems have arisen due to reductions in semiconductor integrated circuit yield. According to one method for improving yield, two vias connecting between wiring arranged in different metalization layers of standard cells (hereafter simply referred to as ‘cells’) to be used in a semiconductor integrated circuit are deployed at each connection. As a result, fracture defects of the cells caused by bad connections between metalization layers decreases. A cell designed with increased yield, as the main priority, by arranging a plurality of vias at each connection is referred to as a ‘yield priority cell’.
However, the yield priority cell is often larger than a cell not manufactured by the above method for improving yield. By deploying a plurality of vias at respective connections, the ratio of connections in the metalization layers increases. As a result, regions for deployment of wiring within the cell decrease, thereby reducing connectibility. Here, ‘connectibility’ denotes flexibility in wiring in the semiconductor integrated circuit. Furthermore, an increase in cell size may increase the chip size.
The following method prevents an increase in the chip size. First, automatic cell arrangement is carried out using cells designed with area reduction as the main priority (hereafter referred to as ‘area priority cells’). The area priority cells are then replaced with yield priority cells having the same functionality and characteristics as the area priority cells. In a case where the size of the yield priority cells is larger than the size of the area priority cells, the area priority cells are replaced with the yield priority cells, using regions that do not include any cells.
The above method does not decrease connectibility due to use of the yield priority cells. Therefore, wiring in the semiconductor integrated circuit, after cell replacement, may be impossible. According to a method taking connectibility after cell replacement into consideration, detailed routes for wiring are designed after a rough arrangement of wiring, and a degree of wiring congestion is estimated base on the results of the calculation. However, rough arrangement of wiring is carried out by a heuristic algorithm based on an enormous amount of information including information of wiring routes, information of cells existing in candidate places for wiring routes, and the like. Therefore, rough arrangement of wiring is time consuming.